1. Field of the Invention
This invention relates to an integrated circuit embodying a phase-locked loop ("PLL") and, more particularly, to a mechanism for controlling frequency of an output signal forwarded from the PLL whenever the PLL is unlocked.
2. Description of the Related Art
A PLL is generally used in many areas of electronics to control the frequency and/or phase of a signal. Instances of use include, for example, applications in frequency synthesizers, analog-digital modulators and demodulators, and clock recovery circuits.
Clock recovery is a term generally used to describe the derivation of a clocking signal. The clocking signal is produced without having to add a timing reference to the circuit which requires the clocking signal. Clock recovery circuits therefore arise when deriving a clocking signal from data transmitted across a communication channel or network. As the stream of data flows across the channel, the clocking signal is constructed and synchronized from transitions of the data. Thus, timing information (i.e., the clocking signal) is recovered from a data stream at the receiving end of, for example, a fiberoptic transmission channel. Avoidance in having to add a separate clock transmission medium or a clock generation circuit at the receiving end circuit is paramount as to the reasons for clock recovery in general.
The PLL compares the arrival of signal transitions on the incoming data stream with the PLL internally generated clock to increase or decrease frequency of the output signal produced from the PLL. Comparison of frequency and phase continues until the incoming data stream can be correctly decoded. Once the correct data is decoded, the PLL is said to be "locked". More specifically, a PLL is considered locked if the phase and/or frequency difference between the incoming data transitions and the PLL internally generated clock is equal or constant with time. If the PLL does not contain an internal clock divider within its feedback loop, then a locked PLL is one that implies an equal frequency and phase between the incoming data frequency (i.e., input signal frequency) and a clocking signal output from the PLL (i.e., output signal frequency).
For robust operation, the PLL must be designed so that it can operate over a wide frequency lock range. A wide range is needed to ensure that the PLL can lock to the input signal data under almost all possible conditions of component variations within the PLL circuit. This wide frequency lock range can produce a wide range of clock frequencies produced at the PLL output. On the other hand, a digital processor connected to receive the PLL output clocking signal will require the output clocking signal frequency not exceed the maximum operating frequency of the processor. Therefore, the recovered clock (i.e., output signal produced by the PLL) must be one which can be controlled so that it does not exceed the maximum operating frequency of the processor if short- and long-term variations in the incoming data stream phase and/or frequency occur.
The incoming data stream to a PLL can oftentimes be temporarily disrupted by, for example, noise placed on the transmission channel. Noise of relatively short duration can in most instances be removed by a low pass filter arranged within the PLL. It is not until, however, several sequential data bits change in phase and/or frequency that the low pass filter can no longer discern and therefore filter that variation.
One example of a relatively long-term variation is shown in reference to FIG. 1. In particular, an optical connector 10 is shown connected to one end of a fiberoptic cable 12. Cable 12 comprises a cylindrical core 14 arranged in contact with the inner surface of a cladding material 16. Core 14 is made of a transparent dielectric material having a refractive index preferably greater than cladding 16.
Connector 10 includes a mechanical attachment mechanism 18 for securing it to cable 12. Connector 10 houses at least one photodetector 20. Photodetector 20 includes any device capable of accepting light energy and converting into an electrical signal. Popular photodetectors include solid state devices, such as silicon photodiodes, phototransistors, and photo-Darlingtons.
To ensure accurate reproduction, coupling between connector 10 and cable 12 must be carefully and precisely made. Special connectors have been designed to mechanically mate and align the transmission path of cable 12 to its respective photodetector 20. Those connectors afford multiple connect and disconnect while maintaining proper alignment in the interim. Unfortunately, each time connector 10 is displaced from cable 12, the phase read by photodetector 20 of any data forwarded through cable 12 changes. Thus, only minor change in the spatial relationship between photodetector 20 and the distal end of cable 12 modify the phase and/or frequency recorded by photodetector 20. If the distance between photodetector 20 and cable 12 is altered (e.g., by disconnect or connect) while data stream 22 is being transmitted, the integrity of data stream 22 may be corrupted. Incorrectly formed transitions of data stream 22 which last for a sufficiently long time are, unfortunately, recorded by the PLL which then attempts to recover a clocking signal based on those transitions.
A relatively long duration of corrupted data cannot be removed by the low pass filter, and will instead cause the PLL clocking signal frequency to rapidly rise or fall. The clocking signal output from the PLL is, unfortunately, forwarded to digital circuits at the receive end of the fiberoptic cable. For example, the digital circuits may include a digital processor which is intended to operate within a pre-defined operating frequency. If the PLL clocking signal (forwarded as an output signal from the PLL) as presented to the digital processor clock input exceeds the maximum frequency of that processor, then the processor will malfunction.